1. Field of the Invention
This invention relates to a pattern correction apparatus, a pattern correction program, a pattern correction method and a fabrication method for a semiconductor device which are utilized in a fabrication process of a semiconductor device.
2. Description of the Related Art
In recent years, as a result of progress of the generation of the basic size of semiconductor devices to that later than the 65-nm generation, the magnitude of the dispersion of the pattern size, the distortion of the shape and so forth which are caused by an influence of proximity effects cannot be ignored any more. Such proximity effects include not only an optical proximity effect which occurs in an optical exposure transfer step but also a process proximity effect which occurs in various semiconductor lithography steps after formation of a resist pattern such as a resist slimming step, a dry etching step and a CMP (Chemical Mechanical Polishing) step. However, under present conditions, while an established highly accurate dimensional correction technique called OPC (Optical Proximity effect Correction) is available against the optical proximity effect, a highly accurate dimensional correction technique applicable to individual steps is not established as yet against the process proximity effect.
For correction calculation of the OPC, two OPC methods are available including a rule-base OPC method and a model-based OPC method. According to the rule-base OPC method, correction calculation is carried out using a one-dimensional dimension such as a pattern line width, a space width or the like of an inputted design pattern as an argument. Meanwhile, according to the model-based OPC, correction calculation is carried out based on a two-dimensional area distribution of peripheral patterns. Although the latter may require longer calculation time than the former, it provides a higher degree of accuracy in dimensional correction because it executes precise calculation. Therefore, for a layer for which the highest degree of accuracy in dimension may be required in a semiconductor circuit such as, for example, a gate layer, selective use of the model-based OPC is increasing in order to perform correction against the optical proximity effect. A related technique is disclosed, for example, in Japanese Patent Laid-Open No. 2004-61720 and Japanese Patent Laid-Open No. 2005-55563.
On the other hand, as regards the process proximity effect, a correlation between the trend of the dimensional dispersion caused by the effect and the two-dimensional area distribution of peripheral patterns is not grasped sufficiently. Therefore, under present conditions, rule-based one-dimensional OPC correction is frequently carried out alternatively based on a corresponding relationship between the level of the line width, space width and so forth of a test pattern and CD (Critical Dimension) measurement values.